Publications of Pascal SAINRAT
Alban Gruin, Thomas Carle, Christine Rochange, Hugues Cassé, Pascal Sainrat
MINOTAuR: a Timing Predictable RISC-V Core Featuring Speculative Execution
IEEE Transactions on Computers, 2023, 72 (1), pp.183-195. ⟨10.1109/TC.2022.3200000⟩
Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quinones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore
ACM Transactions on Embedded Computing Systems (TECS), 2016, 15 (3), ⟨10.1145/2910589⟩
Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer
RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor
In : Computer Systems Science & Engineering, CRL Publishing, Leicester – UK, Special issue Real-Time Systems, Vol. 26 N. 6, pp. 20-36, November 2011.
Theo Ungerer, Francisco Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Hugues Cassé, Christine Rochange, Eduardo Quinones, Sascha Uhrig, Mike Gerdes, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische, Marco Paolieri, Julian Wolf
MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability
In : IEEE Micro, IEEE : Institute of Electrical and Electronics Engineers, Special issue European Multicore Processing Projects, Vol. 30 N. 5, pp. 66-75, September 2010.
Jonathan Barre, Christine Rochange, Pascal Sainrat
Architecture dun processeur multiflot orienté temps-réel
In : Technique et Science Informatiques (TSI), Hermès Science, Special issue SympA’08, Vol. 29, N. 2, pp. 157-178, February 2010.
Christine Rochange, Pascal Sainrat
A Context-Parameterized Model for Static Analysis of Execution Times
In : Transactions on High-Performance Embedded Architecture and Compilation, Springer, Vol. 2 N. 3, pp. 109-128, January 2009.
Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O’Boyle, Dionisos Pnevmatikatos, Alex Ramirez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
High-Performance Embedded Architecture and Compilation Roadmap
In : Transactions on High-Performance Embedded Architecture and Compilation, Springer, Vol. 1 N. 1, pp. 5-29, January 2007.
Christine Rochange, Pascal Sainrat
Régulation du flot d’instructions pour des processeurs orientés temps-réel
In : Technique et Science Informatiques, Lavoisier, Cachan, Vol. 24, N. 8, pp. 963-989, 2005.
Thierry Haquin, Christine Rochange, Pascal Sainrat
CBSP: A Predictor of Sequences of Correlated Branches
In : Computing Letters (CoLe), Brill Academic Publishers, Leiden, The Netherlands, Vol. 1 N. 1, pp. 15-29, January 2005.
Thierry Haquin, Philippe Reynes, Christine Rochange, Pascal Sainrat
Optimisation du chargement des instructions
In : Technique et Science Informatiques, Lavoisier, Vol. 22, N. 6, pp. 689-711, 2003.
Antoine Colin, Isabelle Puaut, Christine Rochange, Pascal Sainrat
Calcul de majorants de pire temps d’exécution : état de l’art
In : Technique et Science Informatique, Lavoisier, Vol. 22, N. 5, pp. 651-677, 2003.
Hugues Cassé, Louis Féraud, Christine Rochange, Pascal Sainrat
Une approche pour réduire la complexité du flot de contrôle dans les programmes C
In : Technique et science informatiques, Hermès, Vol. 21, N. 7, pp. 1009-1032, 2002.
Dominique Lavenier, Daniel Litaize, Pascal Sainrat, Jean-Michel Muller
Et demain, quel PC ?
In : Technique et science informatiques, Hermès, Vol. 20, pp. 111-120, January 2001.
Hugues Cassé, Louis Féraud, Christine Rochange, Pascal Sainrat
Using Abstract Interpretation Techniques for Static Pointer Analysis
In : Computer Architecture News, ACM, ISSN 0163-5694, Vol. 27 N. 1, pp. 47-50, March 1999.
Abstract URL : http://www.irit.fr/publis/APARA/March/208.ps.gz
BibTeXChristine Rochange, Ph. T. Hai, Pascal Sainrat, Daniel Litaize
Préchargement de données dans les caches
In : Technique et Science Informatiques, Hermès, Vol. 16, N. 4, pp. 425-456, April 1997.
Per Stenström, Pascal Sainrat, Christine Rochange
Conception de la mémoire dans les multiprocesseurs à mémoire partagée
In : Calculateurs Parallèles, Vol. 6, N. 3, pp. 83-136, 1994.
Daniel Litaize, Omar Hammami, Mustapha Lalam, Abdelaziz M’zoughi, Pascal Sainrat
Multiprocessors with a serial multiport memory and a pseudo-crossbar of serial links used as a processor-memory switch
In : Computer Architecture News, ACM, Vol. 17 N. 6, pp. 8-21, December 1989.
Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat
Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators
21st International Workshop on Worst-Case Execution Time Analysis (WCET 2023), Jul 2023, Vienne, Austria. pp.2:1-2:12, ⟨10.4230/OASIcs.WCET.2023.2⟩
Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat
Enabling timing predictability in the presence of store buffers
31st International Conference on Real-Time Networks and Systems (RTNS 2023), Jun 2023, Dortmund, Germany. pp.1-10, ⟨10.1145/3575757.3593653⟩
Hugues Cassé, Emmanuel Caussé, Pascal Sainrat
Verification of SimNML instruction set description using co-simulation
2nd RISC-V Meeting 2019, Institut de recherche technologique Nanoelec, Grenoble, France; Commissariat à l’énergie atomique et aux énergies alternatives (CEA), France, Oct 2019, Paris, France
Architecture des processeurs pour les systèmes critiques – Haute performance et prédictibilité
13ème Colloque. du Groupe de Recherche System on Chip – GdR SoC/SiP 2018, Jun 2018, Paris, France
Quentin Perret, Pascal Maurere, Eric Noulard, Claire Pagetti, Pascal Sainrat, Benoît Triquet
Mapping hard real-time applications on many-core processors
24th International Conference on Real-Time and Network Systems (RTNS 2016), Oct 2016, Brest, France. pp. 235-244
Quentin Perret, Pascal Maurere, Eric Noulard, Claire Pagetti, Pascal Sainrat, Benoît Triquet
Temporal isolation of hard real-time applications on many-core processors
RTAS 2016 – IEEE Real-Time Embedded Technology & Applications Symposium, Apr 2016, Vienne, Austria. pp. 1-11, ⟨10.1109/RTAS.2016.7461363⟩
Quentin Perret, Pascal Maurère, Éric Noulard, Claire Pagetti, Pascal Sainrat, Benoît Triquet
Predictable composition of memory accesses on many-core processors
8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), Jan 2016, TOULOUSE, France
Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quinones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka
Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core
3rd Workshop on High-performance and Real-time Embedded Systems (HiRES 2015) in conjunction with HiPEAC 2015, Luís Miguel Pinho, CISTER, Portugal; Eduardo Quiñones, BSC, Spain; Sascha Uhrig, TU Dortmund, Germany, Jan 2015, Amsterdam, Netherlands
Haluk Ozaktas, Christine Rochange, Pascal Sainrat
Minimizing the Cost of Synchronisations in the WCET of Real-Time Parallel Programs
17th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2014), Jun 2014, Sankt Goar, Germany. pp.98-107, ⟨10.1145/2609248.2609261⟩
Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, Joao Fernandes, Zaykov Pavel, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, Ian Broster, David George, Eduardo Quinones, Milos Panic, Francisco Cazorla, Jaume Abella, Sascha Uhrig, Mathias Rohde, Arthur Pyka
parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability (regular paper)
In : Euromicro Conference on Digital System Design (DSD 2013), Santander (Spain), 04/09/13-06/09/13, IEEE : Institute of Electrical and Electronics Engineers, pp. 363-370, September 2013.
Hugues Cassé, Florian Birée, Pascal Sainrat
Multi-architecture Value Analysis for Machine Code (regular paper)
In : Workshop on Worst-Case Execution Time Analysis, Paris, 09/07/13, OASICs, Dagstuhl Publishing, pp. 42-52, July 2013.
Haluk Ozaktas, Christine Rochange, Pascal Sainrat
Automatic WCET Analysis of Real-Time Parallel Applications (regular paper)
In : Workshop on Worst-Case Execution Time Analysis, Paris, 09/07/13, OASICs, Dagstuhl Publishing, pp. 11-20, July 2013.
Roman Bourgade, Christine Rochange, Pascal Sainrat
Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets (regular paper)
In : International Conference on Architecture of Computing Systems (ARCS 2012), Prague, 19/02/12-23/02/13, Springer, pp. 341-351, February 2013.
Hicham Agrou, Pascal Sainrat, Marc Gatti, Patrice Toillon
Mastering The Behavior of Multi-Core Systems to Match Aviation Requirements (regular paper)
In : Digital Avionics Systems Conference (DASC 2012), Williamsburg, VA, USA, 14/10/12-18/10/12, Vol. 6E5, IEEE : Institute of Electrical and Electronics Engineers, pp. 1-12, October 2012.
Abstract URL : http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6382403
BibTeXMike Gerdes, Florian Kluge, Theo Ungerer, Christine Rochange, Pascal Sainrat
Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications (regular paper)
In : Design, Automation and Test in Europe (DATE 2012), Dresden, 12/03/12-16/03/12, IEEE : Institute of Electrical and Electronics Engineers, pp. 671-676, March 2012.
Hicham Agrou, Marc Gatti, Pascal Sainrat, Patrice Toillon
Multi-Core Architectures
In : Certification Together International Conference, Toulouse, 29/11/11-01/12/11.
Hicham Agrou, Marc Gatti, Pascal Sainrat, Patrice Toillon
A Design Approach for Predictable and Efficient Multi-Core Processor for Avionics (regular paper)
In : Digital Avionics Systems Conference (DASC 2011), Seattle, 16/10/11-20/10/11, Vol. 7D3, IEEE : Institute of Electrical and Electronics Engineers, pp. 1-11, October 2011 (Session Best Paper).
Abstract URL : http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6096128
BibTeXChristine Rochange, Pascal Sainrat
Multicores and Critical Systems: Challenges for Temporal Analysability
In : SAE AeroTech Congress & Exhibition, Toulouse, 18/10/11-21/10/11.
Roman Bourgade, Christine Rochange, Pascal Sainrat
Predictable Bus Arbitration Schemes for Heterogeneous Time-Critical Workloads Running on Multicore Processors (short paper)
In : Emerging Technologies and Factory Automation (ETFA 2011), Toulouse, 05/09/11-09/09/11, IEEE : Institute of Electrical and Electronics Engineers, pp. 1-4, September 2011.
Abstract URL : http://www.irit.fr/publis/TRACES/12619_etfa2011.pdf
BibTeXHugues Cassé, Jonathan Barre, Rodolphe Vaillant-David, Pascal Sainrat
Fast Instruction-Accurate Simulation with SimNML (regular paper)
In : Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO 2011), Heraklion, Crète, Grèce, 22/01/11, Université de Lille, pp. 8-12, January 2011.
URL : http://www.irit.fr/publis/TRACES/12161_rapido2011.pdf
BibTeXClément Ballabriga, Hugues Cassé, Christine Rochange, Pascal Sainrat
OTAWA: an Open Toolbox for Adaptive WCET Analysis (regular paper)
In : IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2010), Waidhofen/Ybbs, Austria, 13/10/10-15/10/10, Springer, pp. 35-46, October 2010.
URL : http://www.irit.fr/publis/TRACES/11771_seus2010.pdf
BibTeXChristine Rochange, Armelle Bonenfant, Pascal Sainrat, Mike Gerdes, Julian Wolf, Theo Ungerer, Zlatko Petrov, Frantisek Mikulu
WCET Analysis of a Parallel 3G Multigrid Solver Executed on the MERASA Multi-core (regular paper)
In : International Workshop on Worst-Case Execution Time Analysis (WCET 2010), Brussels, 06/07/10, Vol. 268, Björn Lisper (Eds.), Austrian Computer society, pp. 92-102, July 2010.
URL : http://www.irit.fr/publis/TRACES/11647_wcet2010.pdf
BibTeXRoman Bourgade, Christine Rochange, Marianne De Michiel, Pascal Sainrat
MBBA: a Multi-Bandwidth Bus Arbiter for hard real-time (regular paper)
In : International Conference on Embedded and Multimedia Computing (EMC 2010), Cebu, Philippines, 11/08/10-13/08/10, IEEE : Institute of Electrical and Electronics Engineers, pp. 1-8, August 2010 (Best paper).
URL : http://www.irit.fr/publis/TRACES/11588_emc2010-bourgade-final.pdf
BibTeXHugues Cassé, Pascal Sainrat, Clément Ballabriga, Marianne De Michiel
Experimentation of WCET computation on both ends of automotive processor range (regular paper)
In : Workshop on Critical Automotive applications: Robustness and Safety (CARS 2010), Valencia, Spain, 27/04/10, ACM : Association for Computing Machinery, pp. 67-70, May 2010.
URL : http://www.irit.fr/publis/TRACES/11476_cars2010.pdf
BibTeXJulian Wolf, Mike Gerdes, Sascha Uhrig, Jörg Mische, Florian Kluge, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer
RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-Core Processor (regular paper)
In : International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2010), Carmona, Spain, 05/05/10-06/05/10, IEEE : Institute of Electrical and Electronics Engineers, pp. 193-201, May 2010.
URL : http://www.irit.fr/publis/TRACES/11376_isorc2010.pdf
BibTeXTahiry Ratsiambahotra, Hugues Cassé, Pascal Sainrat
A Versatile Generator of Instruction Set Simulators and Disassemblers
In : International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS 2009), Istanbul, Turkey, 13/07/09-16/07/09, IEEE : Institute of Electrical and Electronics Engineers, pp. 65-72, July 2009.
URL : http://www.irit.fr/publis/TRACES/10727_spects09.pdf
BibTeXNiklas Holsti, Jan Gustafsson, Guillem Bernat, Clément Ballabriga, Armelle Bonenfant, Roman Bourgade, Hugues Cassé, Daniel Cordes, Albrecht Kadlec, Raimund Kirner, Jens Knoop, Paul Lokuciejewski, Nicholas Merriam, Marianne De Michiel, Adrian Prantl, Bernhard Rieder, Christine Rochange, Pascal Sainrat, Markus Schordan
WCET Tool Challenge 2008: report
In : International Workshop on Worst-Case Execution Time Analysis (WCET 2008), Prague, 01/07/08-01/07/08, Austrian Computer society, pp. 149-171, October 2008.
URL : http://www.irit.fr/publis/TRACES/9687_challenge08.pdf
BibTeXArmelle Bonenfant, Marianne De Michiel, Pascal Sainrat
oRange: A Tool For Static Loop Bound Analysis
In : Workshop on Resource Analysis, University of Hertfordshire, Hatfield, UK, 09/09/08.
URL : http://www.irit.fr/publis/TRACES/9686_workshop_resource_analysis_2008.pdf
BibTeXRoman Bourgade, Clément Ballabriga, Hugues Cassé, Christine Rochange, Pascal Sainrat
Accurate analysis of memory latencies for WCET estimation (regular paper)
In : International Conference on Real-Time and Network Systems (RTNS 2008), Rennes, 16/10/08-17/10/08, IRISA, pp. 161-170, October 2008.
URL : http://www.irit.fr/publis/TRACES/9445_rtns08final.pdf
BibTeXMarianne De Michiel, Armelle Bonenfant, Hugues Cassé, Pascal Sainrat
Static loop bound analysis of C programs based on flow analysis and abstract interpretation
In : IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2008), Kaohsiung, Taiwan, 25/08/08-27/08/08, IEEE Computer Society, pp. 161-168, August 2008.
Abstract URL : http://www.irit.fr/publis/TRACES/9176_rtcsa_2008_publie_michiel-loopbounds.pdf – http://www.irit.fr/publis/TRACES/9176_rtcsa_2008_michiel-loopbound-slides.pdf
BibTeXFadia Nemer, Hugues Cassé, Pascal Sainrat, Jean-Paul Bahsoun
Inter-Task WCET computation for A-way Instruction Caches
In : IEEE International Symposium on Industrial Embedded Systems (SIES 2008), Montpellier, 11/06/08-13/06/08, IEEE : Institute of Electrical and Electronics Engineers, pp. 193-200, June 2008.
URL : http://www.irit.fr/publis/TRACES/9093_sies_08.pdf
BibTeXJonathan Barre, Christine Rochange, Pascal Sainrat
An Architecture for the Simultaneous Execution of Hard Real-Time Threads
In : International Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation (IC-SAMOS 2008), Samos, 21/07/08-24/07/08, IEEE : Institute of Electrical and Electronics Engineers, pp. 18-24, July 2008.
URL : http://www.irit.fr/publis/TRACES/9071_samos2008.pdf
BibTeXTahiry Ratsiambahotra, Hugues Cassé, Christine Rochange, Pascal Sainrat
Génération automatique de simulateurs fonctionnels de processeurs
In : Symposium sur les Architectures Nouvelles de Machines (SympA 2008), Fribourg, 11/02/08-13/02/08, Ecole d’ingénieurs et d’architectes de Fribourg, (electronic medium), February 2008.
URL : http://hal.archives-ouvertes.fr/action/open_file.php?url=http://hal.archives-ouvertes.fr/docs/00/20/23/28/PDF/RaCaRoSa2008.1.pdf&docid=202328
BibTeXJonathan Barre, Christine Rochange, Pascal Sainrat
Une architecture SMT pour le temps-réel strict
In : Symposium sur les Architectures Nouvelles de Machines (SympA 2008), Fribourg, 11/02/08-13/02/08, Ecole d’ingénieurs et d’architectes de Fribourg, (electronic medium), February 2008.
URL : http://www.irit.fr/publis/TRACES/8558_sympa2008.pdf
BibTeXJonathan Barre, Christine Rochange, Pascal Sainrat
A Predictable Simultaneous Multithreading Scheme for Hard Real-Time
In : International Conference on Architecture of Computing Systems (ARCS 2008), Dresden, 25/02/08-28/02/08, Springer, LNCS 4934, pp. 161-172, February 2008 (Best Paper).
URL : http://www.irit.fr/publis/TRACES/ARCS08-final.pdf
BibTeXClément Ballabriga, Hugues Cassé, Pascal Sainrat
An improved approach for set-associative instruction cache partial analysis
In : Annual ACM Symposium on Applied Computing (SAC 2008), Fortaleza (Brazil), 16/03/08-20/03/08, ACM : Association for Computing Machinery, pp. 360-368, March 2008.
Abstract URL : http://www.irit.fr/publis/TRACES/8311_sac08.pdf
BibTeXFadia Nemer, Hugues Cassé, Pascal Sainrat, Ali Awada
Improving the WCET accuracy by inter-task instruction cache analysis
In : IEEE International Symposium on Industrial Embedded Systems (SIES 2007), Lisbonne, 04/07/07-06/07/07, IEEE : Institute of Electrical and Electronics Engineers, pp. 25-32, July 2007.
URL : http://www.irit.fr/publis/TRACES/7839_SIES07.pdf
BibTeXClément Ballabriga, Hugues Cassé, Pascal Sainrat
WCET computation on software components by partial static analysis
In : Junior Researcher Workshop on Real-Time Computing, Nancy, 29/03/07-30/03/07, LORIA, pp. 15-18, March 2007.
Abstract URL : http://www.irit.fr/publis/TRACES/7790_JRWRTC07.pdf
BibTeXHugues Cassé, Christine Rochange, Pascal Sainrat
On the sensitivity of WCET estimates to the variability of basic blocks execution times
In : International Conference on Real-Time and Network Systems (RTNS 2007), Nancy, 29/03/07-30/03/07, INPL, pp. 85-92, March 2007.
Abstract URL : http://www.irit.fr/publis/TRACES/7547_rtns07.pdf
BibTeXJonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat
Calcul de temps d’exécution pire cas pour un processeur superscalaire à exécution non ordonnée
In : Symposium sur les Architectures Nouvelles de Machines (SympA 2006), Perpignan, 04/10/06-06/10/06, Université de Perpignan, pp. 1-11, October 2006.
URL : http://www.irit.fr/publis/TRACES/6738_sympa9.pdf
BibTeXFadia Nemer, Hugues Cassé, Pascal Sainrat, Jean-Paul Bahsoun, Marianne De Michiel
PapaBench : A Free Real-Time Benchmark
In : International Workshop on Worst-Case Execution Time Analysis (WCET 2006), Dresden, 04/07/06, Frank Mueller (Eds.), Dagstuhl Research Online Publication Server, (on line), July 2006.
Abstract URL : http://www.irit.fr/publis/TRACES/6680_papabench_wcet2006.pdf
BibTeXCombining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis
In : International Workshop on Worst-Case Execution Time Analysis (WCET 2006), Dresden, 04/07/06, Dagstuhl Research Online Publication Server, (on line), July 2006.
Abstract URL : http://drops.dagstuhl.de/opus/volltexte/2006/675/pdf/WCET_Kebbal.675.pdf
BibTeXJonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat
Modeling Instruction-Level Parallelism for WCET Evaluation
In : IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), Sidney, 16/08/06-18/08/06, IEEE : Institute of Electrical and Electronics Engineers, pp. 61-67, August 2006.
Abstract URL : http://www.irit.fr/publis/TRACES/6668_rtcsa06.pdf
BibTeXChristine Rochange, Pascal Sainrat
Code padding to improve the WCET calculability
In : International Conference on Real-Time and Network Systems (RTNS 2006), Poitiers, 30/05/06-31/05/06, LISI-ENSMA, pp. 159-168, May 2006.
Abstract URL : http://www.irit.fr/publis/TRACES/rtns06.pdf
BibTeXOTAWA, a framework for experimenting WCET computations
In : European Congress on Embedded Real-Time Software (ERTS 2006), Toulouse, 25/01/06-27/01/06, Société de l’Electricité, de l’Electronique et des Technologies de l’Information et de la Communication (SEE), (electronic medium), January 2006.
Abstract URL : http://www.irit.fr/publis/TRACES/6278_ERTS06.pdf
BibTeXClaire Burguiere, Christine Rochange, Pascal Sainrat
A Case for Static Branch Prediction in Real-Time Systems
In : 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Hong-Kong, 17/08/05-19/08/05, IEEE, pp. 33-38, August 2005.
Abstract URL : http://www.irit.fr/publis/TRACES/5834_rtcsa.pdf
BibTeXProcesseurs haute performance
In : Ecole thématique en Architectures des systèmes matériels enfouis et méthodes de conception associées (ARCHI’05), Autrans, 21/03/05-25/03/05, Arnaud Tisserand (Eds.).
Christine Rochange, Pascal Sainrat
A Time-Predictable Execution Mode for Superscalar Pipelines with Instruction Prescheduling
In : ACM International Conference on Computing Frontiers, Ischia, Italy, 04/05/05-06/05/05, ACM : Association for Computing Machinery, pp. 307-314, May 2005.
Abstract URL : http://www.irit.fr/publis/TRACES/5143_CF05.pdf – http://www.irit.fr/publis/TRACES/5143_slidesCF05.pdf
BibTeXChristine Rochange, Pascal Sainrat
Vers une prédictibilité temporelle des processeurs haute-performance
In : 12th International Conference on Real-Time Systems, Paris, 30/03/04-01/04/04, BIRP, pp. 282-300, March 2004.
Abstract URL : http://www.irit.fr/publis/TRACES/5338_rts04.pdf
BibTeXHugues Cassé, Christine Rochange, Pascal Sainrat
An Open Framework for WCET Analysis
In : IEEE Real-Time Systems Symposium – WIP session, Lisbonne, 05/12/04-07/12/04, IEEE, pp. 13-16, December 2004.
Christine Rochange, Pascal Sainrat
Towards Designing WCET-predictable Processors
In : 3rd Workshop on Worst-Case Execution Time Analysis, Porto, 01/07/03, –, pp. 87-90, July 2003.
Abstract URL : http://www.irit.fr/publis/TRACES/3840_wcet2003.pdf
BibTeXChristine Rochange, Pascal Sainrat
Difficulties in Computing the WCET for Processors with Speculative Execution
In : 2nd Intl. Workshop on Worst Case Execution Time Analysis, Vienne, 18/06/02, University of York, pp. 68-71, June 2002.
Abstract URL : http://www.irit.fr/publis/TRACES/3292_wcet2002.pdf
BibTeXPhilippe Reynes, Thierry Haquin, Christine Rochange, Pascal Sainrat
Etude préparatoire à la réutilisation de chaînes
In : 8ème Symposium en Architectures Nouvelles de Machines (SYMPA’8), Hammamet, Tunisie, 10/04/02-12/04/02, Ecole supérieure des sciences et techniques de Tunis, pp. 365-372, April 2002.
Abstract URL : http://www.irit.fr/publis/APARA/March/3115.ps.gz
BibTeXThierry Haquin, Philippe Reynes, Christine Rochange, Pascal Sainrat
Optimisations du chargement des instructions
In : 8ème Symposium en Architectures Nouvelles de Machines (SYMPA’8), Hammamet, Tunisie, 10/04/02-12/04/02, Ecole Supérieure des Sciences et Techniques de Tunis, pp. 257-264, April 2002.
Abstract URL : http://www.irit.fr/publis/APARA/March/3114.pdf.gz
BibTeXPascal Sainrat, Olivier Sentieys
Conférence invitée : DSP et processeurs superscalaires : la convergence ?
In : ASTI’2001 – SYMPA 7 : 7ème symposium en architectures de machines, Paris, 24/04/01-27/04/01, INRIA, pp. 191, April 2001.
De l’architecture des ordinateurs à la détermination de temps d’exécution maximum
In : Séminaire, LAAS, 29/03/01.
Pascal Sainrat, Bernard Lecussan
Architecture du noeud d’une grappe de processeurs
In : Ecole thématique iHPerf2000, Aussois, France, 04/12/00-08/12/00.
Architecture des processeurs superscalaires
In : Ecole thématique du CNRS sur la conception d’architectures de systèmes informatiques dédiés à des applications spécifiques de type “enfoui”, Seix, France, 20/11/00-23/11/00.
URL : http://www.ens-lyon.fr/LIP/Ecoles_Archi/sainrat.pdf
BibTeXThierry Haquin, Christine Rochange, Pascal Sainrat
Une extension de la résolution partielle dans les BTBs
In : 6ème Symposium sur les Architectures Nouvelles de Machines (SYMPA’6), Besançon, 19/06/00-22/06/00, Université de Besançon, France, pp. 77-86, June 2000.
Carmen Turinici, Christine Rochange, Pascal Sainrat
Prédicteurs mixtes pour l’anticipation des instructions
In : 5ème Symposium sur les Architectures Nouvelles de Machines (SYMPA’5), Rennes, 08/06/99-11/06/99, INRIA, pp. 165-174, June 1999.
Christine Rochange, Pascal Sainrat, Louis Féraud, Hugues Cassé
Using Abstract Interpretation Technics for Static Pointer Analysis
In : 3rd workshop on Interaction Between Compilers and Computer Architectures (INTERACT’3), San Jose, USA, 03/10/99-07/10/99, Pen-Chung Yew, University of Minnesota, October 1999.
Abstract URL : http://www.irit.fr/publis/APARA/March/A_Interact3.ps.gz
BibTeXCarmen Turinici, Christine Rochange, Pascal Sainrat
Instruction Reuse Based on Dependent Instruction Sequences
In : 6th International Symposium on Automatic Control and Computer Engineering (SACCS’98), Iasi, Roumanie, 20/11/98-21/11/98, D. Grigoras, Matrix Rom Publ., Bucharest, pp. 134-139, November 1998.
Christine Rochange, Pascal Sainrat
Evaluation de performances des processeurs superscalaires
In : Colloque Outils et Méthodologies pour l’Architecture des Ordinateurs, Orsay, France, 22/09/98-23/09/98.
Daniel Litaize, Pascal Sainrat
Communications in Shared-Memory Multiprocessors
In : International Workshop on New Technologies, Interconnects and Communications in Distributed and Parallel Systems, Toulouse, 16/06/97-17/06/97.
H. Pham Tuong, Christine Rochange, Pascal Sainrat, Daniel Litaize
Prédiction de l’adresse des lectures pour tolérer la latence des accès mémoire
In : 9èmes Rencontres du Parallélisme (RenPar9), Lausanne, -, pp. 181-184, May 1997.
Abstract URL : http://www.irit.fr/publis/APARA/March/A_Renpar9.ps.gz
BibTeXPascal Sainrat, Stephan Jourdan, Daniel Litaize
Tampons d’amorçage des microprocesseurs superscalaires à exécution non ordonnée : une analyse
In : 8èmes Rencontres du Parallélisme, Bordeaux, -, pp. 121-124, May 1996.
Abstract URL : http://www.irit.fr/publis/APARA/March/A_Renpar8_1.ps.gz
BibTeXAndré Seznec, Stephan Jourdan, Pascal Sainrat, P. Michaud
Multiple-Block Ahead Branch Predictors
In : 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), Cambridge, Massachusetts, ACM, pp. 116-127, October 1996.
Abstract URL : http://www.irit.fr/publis/APARA/March/A_Asplos7.ps.gz
BibTeXDaniel Litaize, Pascal Sainrat
Consequences of the use of ultra high speed serial links as memory-processors and memory-I/O networks in shared-memory multiprocessor and vector supercomputers
In : Workshop franco-americano-suédois on Computer Architecture, Ecole Polytechnique de Palaiseau, .
Stephan Jourdan, Pascal Sainrat
Analyse de l’impact des dépendances de données
In : 7èmes Rencontres du Parallélisme, Mons, Belgique, -, pp. 32-36, May 1995.
URL : http://www.irit.fr/publis/APARA/Superscalar/P_Renpar7.ps.gz
BibTeXStephan Jourdan, Pascal Sainrat
Parallélisme potentiel de grain fin des programmes d’évaluation SPEC92
In : 4ème symposium sur les Architectures Nouvelles de Machines, Rennes, -, pp. 97-106, December 1995.
URL : http://www.irit.fr/publis/APARA/March/S_PRCANM4.ps.gz
BibTeXStephan Jourdan, Pascal Sainrat, Daniel Litaize
Is symmetry Really Worthwhile ?
In : 21st Euromicro Conference: Design of Hardware/Software Systems, –, IEEE Computer Society press, Los Alamitos, California, pp. 196-203, September 1995.
Abstract URL : http://www.irit.fr/publis/APARA/March/A_Euromicro94.ps.gz
BibTeXStephan Jourdan, Pascal Sainrat, Daniel Litaize
An Investigation of the Performance of Various Instruction-Issue Buffer Topologies
In : 28th Annual International Symposium on Microarchitecture (MICRO-28), Ann Arbor, IEEE/ACM, pp. 279-284, December 1995.
Abstract URL : http://www.irit.fr/publis/APARA/March/A_Micro28.ps.gz
BibTeXStephan Jourdan, Pascal Sainrat, Daniel Litaize
Exploring Configurations of Functional Units in an Out-Of-Order Superscalar Microprocessor
In : 22nd International Symposium on Computer Architecture, Santa Margherita Ligure, IEEE-ACM, pp. 117-125, June 1995.
Abstract URL : http://www.irit.fr/publis/APARA/Superscalar/A_ISCA22.ps.gz
BibTeXDominique Carrière, Stephan Jourdan, Daniel Litaize, Christine Rochange, Pascal Sainrat
Le parallélisme de données et d¿instructions dans les multiprocesseurs à mémoire commune
In : Journées sur le parallélisme de l¿IRIT, Toulouse, .
Daniel Litaize, Christophe Guittenit, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Serial Multiported Memory used as a cache disk in I/O subsystems
In : Fourth Workshop on Scalable Shared-Memory Multiprocessors, Chicago, .
Daniel Litaize, Christophe Guittenit, Abdelaziz M’zoughi, Pascal Sainrat
Applications des liaisons série en environnement multiprocesseur à mémoire commune
In : Journées PRC/GDR Architecture de Machines Nouvelles, Orsay, -, pp. 31-36, January 1994.
Daniel Litaize, Dominique Carrière, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Using Ultra High-Speed Serial Links in Shared-Memory Multiprocessors
In : Open Bus Systems ’94, Paris, VITA, pp. 103-110, January 1994.
Daniel Litaize, Dominique Carrière, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Le module mémoire et la liaison série du multiprocesseur M3S
In : Forum des recherches en informatique, Palaiseau, .
Christine Rochange, Pascal Sainrat
Evaluation du multiprocesseur M3S par analyse de la valeur moyenne
In : Journée des jeunes chercheurs en systèmes à mémoire logiquement partagée, Toulouse, .
Daniel Litaize, Abdelaziz M’zoughi, Pascal Sainrat, Dominique Carrière, Christine Rochange
Projet M3S : multiprocesseur à mémoire multiport série
In : Journées ¿Modèles d¿exécution et architectures parallèles¿ ; PRC-ANM, Rennes, .
Dominique Carrière, Daniel Litaize, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Update on the M3S project
In : 3rd Workshop on Scalable Shared-Memory Multiprocessors, San Diego, .
Christine Rochange, Pascal Sainrat, Daniel Litaize
Performance of M3S for the SOR algorithm
In : Conference on Parallel ARchitectures and Languages Europe (PARLE), Munich, Springer, pp. 676-679, June 1993.
Daniel Litaize, Abdelaziz M’zoughi, Pascal Sainrat, Jean-Claude Salinier, Mustapha Lalam
Le projet M3S : multiprocesseur à mémoire multiport série
In : Premières journées du PRC Architectures de machines, Toulouse, .
Daniel Litaize, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
La liaison série à ultra haut débit : une (la?) solution pour les liaisons inter-modules en environnement multiprocesseur
In : Colloque “Technologies Matérielles Futures pour l’ordinateur”, Paris, .
Daniel Litaize, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Towards a shared-memory massively parallel multiprocessor
In : IEEE International Symposium on Computer Architecture, Gold Coast, Australie, IEEE, pp. 70-79, May 1992.
Dominique Carrière, Daniel Litaize, Christine Rochange, Pascal Sainrat
Design of the memory plane of the M3S project
In : International Workshop on Field-Programmable Logic and Applications, Vienne, University of Kaiserslautern, September 1992.
Daniel Litaize, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
The design of the M3S project : a Multiported Shared Memory Multiprocessor
In : Supercomputing, Minneapolis, IEEE, pp. 326-335, November 1992.
Daniel Litaize, Omar Hammami, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Multiprocesseur massivement parallèle à mémoire multiport série
In : Troisième symposium sur les Architectures Nouvelles de Machines, Palaiseau, .
Daniel Litaize, Omar Hammami, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Project M3S : How serial links are well suited for scalability
In : Second Workshop on Scalable Shared Memory Multiprocessors, Toronto, .
Pascal Sainrat, Daniel Litaize
On some technical problems inherent to the use of high-speed digital circuits
In : International Workshop on Parallel Computing, Trani, Italie, -, pp. 194-197, September 1991.
Daniel Litaize, Omar Hammami, Pascal Sainrat, René Pulou
Les liaisons série du multiprocesseur M3S : justification, problèmes techniques, solutions
In : Deuxième symposium sur les Architectures Nouvelles de Machines, Toulouse, .
Daniel Litaize, Fatima-Zahra Elkhlifi, Mustapha Lalam, Abdelaziz M’zoughi, Pascal Sainrat
Présentation de M3S : Multiprocesseur à mémoire multiport série
In : Journées ” Algorithmes parallèles et architectures nouvelles”, Toulouse, .
Daniel Litaize, Fatima-Zahra Elkhlifi, Mustapha Lalam, Abdelaziz M’zoughi, Pascal Sainrat
Multiprocessors with serial multiport memories
In : Conference on Parallel ARchitectures and Languages Europe (PARLE), Eindhoven, The Netherlands, Springer-Verlag (LNCS-365), pp. 34-51, June 1989.
Fatima-Zahra Elkhlifi, Omar Hammami, Mustapha Lalam, Daniel Litaize, Pascal Sainrat
Multiprocessors system with caches, serial multiport memory and pseudo crossbar of serial links
In : Applied Informatics, Grindelwald, Switzerland, -, pp. 167-170, February 1989.
Christine Rochange, Pascal Sainrat
Architecture des machines
In : Encyclopédie de l’informatique et des systèmes d’information. Jacky Akoka, Isabelle Comyn-Wattiau (Eds.) , Vuibert, pp. 147-159, November 2006.
Daniel Litaize, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
Architecture of Parallel and Distributed Systems
In : Handbook in Information Systems, volume 5: Handbook on Parallel and Distributed Processing. J. Blazewicz, K. Ecker, B. Plateau, D. Trystram (Eds.) , Springer-Verlag, pp. 166-221, International Handbooks on Information Systems, 1999.
Daniel Litaize, Omar Hammami, Abdelaziz M’zoughi, Christine Rochange, Pascal Sainrat
La liaison série à ultra haut débit : une (la?) solution pour les liaisons inter-modules en environnement multiprocesseur
In : Technologies Matérielles Futures pour l’ordinateur. – – (Eds.) , Frontières, Paris, pp. 167-177, 1991.
Parallélisme niveau tâche et parallélisme niveau instruction
HDR, Université Paul Sabatier, March 1998.
Réseau d’interconnexion du multiprocesseur M3S : étude et mise en oeuvre
Master’s Thesis, Université Paul Sabatier, January 1991.
Christine Rochange, Sascha Uhrig, Pascal Sainrat
Time-Predictable Architectures, ISTE – WILEY, November 2013.
Computation of Worst Case Execution Time
Tutoriel. October 2010.
Abstract URL : http://www.irit.fr/publis/TRACES/11999_socket_workshop2010.pdf
BibTeXHugues Cassé, Jacques Collet, Yves Crouzet, Christine Rochange, Pascal Sainrat
Maîtriser les temps d’exécution
Vulgarisation. November 2007.
Abstract URL : http://www.ups-tlse.fr/servlet/com.univ.collaboratif.utils.LectureFichiergw?CODE_FICHIER=1196687680965&ID_FICHE=5217
BibTeXL’objet informatisé
Diffusion scientifique. November 2000. Noir sur Blanc, V.1, N.3, p.3-5
URL : http://www.irit.fr/passerelles/NsB/noirsurblanc3.pdf
BibTeXChristine Rochange, Pascal Sainrat, Daniel Litaize
M3S : A Scalable Multiprocessor
Diffusion scientifique. February 1994. TCCA newsletter, IEEE
800 Mbit/s grâce à l’arséniure de gallium
Diffusion scientifique. October 1992. Electronique, le mensuel des ingénieurs de conception, V.21, p.65-70